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[Other resource] pll

Description: 用VHDL写的数字锁相环程序 pll.vhd为源文件 pllTB.vhd为testbench-pll.vhd : PLL written in VHDL hardware language. pllTB.vhd is a test program for pll.vhd.
Platform: | Size: 111853 | Author: 孙犁 | Hits:

[MPI] floatmul

Description: 采用VERILOG 语言进行设计 实现32位浮点数乘法运算 结果已经验证过 放心使用-Verilog design language used to achieve 32-bit floating-point multiplication results have been verified ease of use
Platform: | Size: 1024 | Author: NOVEI | Hits:

[VHDL-FPGA-Verilog] xapp199(E)

Description: vhdl的testbench编写的文档，英文版的，可以看懂-VHDL Testbench for the preparation of documents, in English, you can understand
Platform: | Size: 197632 | Author: xwy | Hits:

[MiddleWare] FinalCodelast

Description: last cordic for immplemantaion of cordic with vhdl language it has testbench
Platform: | Size: 8192 | Author: akhlaghi | Hits:

[VHDL-FPGA-Verilog] myself_uart_vhdl

Description: 自己写的，对串口的VHDL描述，有完整testbench，特别是详细的功能说明和注释。-Wrote it myself, on the serial port of the VHDL description of a complete testbench, in particular, detailed functional descriptions and notes.
Platform: | Size: 6144 | Author: 崔易 | Hits:

[VHDL-FPGA-Verilog] Writing_Efficient_Testbenches

Description: vhdl语言 和verilog hdl语言的测试程序编写- testbench for vhdl and verilog
Platform: | Size: 197632 | Author: kang | Hits:

[VHDL-FPGA-Verilog] i2c.tar

Description: 是个I2C软核，使用verilog和vhdl实现的，含有testbench。-this is soft core of I2C in verilog rtl and VHDL.
Platform: | Size: 702464 | Author: 杨力 | Hits:

[VHDL-FPGA-Verilog] bin2bcd

Description: Binary to BCD converter
Platform: | Size: 1024 | Author: Natacho | Hits:

[VHDL-FPGA-Verilog] shift

Description: Simple shift register with testbench in vhdl
Platform: | Size: 1024 | Author: Tukan | Hits:

[VHDL-FPGA-Verilog] FPGA_Design_Guide_Chapter1_Westor

Description:
Platform: | Size: 2136064 | Author: 陈枫 | Hits:

[VHDL-FPGA-Verilog] divisor_n_bits_sin_restauracion

Description: vhdl divisor of n-bits without restaurecion metod. divisor de nbits en vhdl sin restauracion. con testbench.
Platform: | Size: 1024 | Author: emiliano | Hits:

[Graph program] GUI_Matting

Description: matlab编写的交互式image matting程序，包括：Poisson，Hillman，Ruzon等方法和源图像-matlab interactive image matting procedures, including: Poisson, Hillman, Ruzon methods and sources image
Platform: | Size: 2227200 | Author: andrew | Hits:

[VHDL-FPGA-Verilog] BP062-BU-01000-r0p0-00rel0[1][1].tar

Description: AXI协议检查器，由ARM公司开发对于想开发AXI master和slave模型的ASIC设计人员非常有用！-AXI protocol checker, developed by ARM to develop for the AXI master and slave model is very useful ASIC designers!
Platform: | Size: 313344 | Author: 李忠孝 | Hits:

[VHDL-FPGA-Verilog] SRAM

Description: 瑞芯科技EFX400SL开发板上使用SRAM的工程源码-Rockchip EFX400SL the development of science and technology the use of SRAM on-board source of project
Platform: | Size: 1110016 | Author: 曹晶 | Hits:

[VHDL-FPGA-Verilog] pn_generator

Description: FPGA实现pn发生器，Verilog代码实现，另带modlesim的仿真测试文件，很有价值。-FPGA realization of pn generator, Verilog code, and the other with the simulation test modlesim documents of great value.
Platform: | Size: 3072 | Author: 胡佳 | Hits:

[VHDL-FPGA-Verilog] EDA

Description: VHDL上机手册（基于Xilinx ISE） ___________________________________________________ 1 ISE 软件的运行 2 创建一个新工程 3 创建一个VHDL源文件框架 4 输入VHDL程序 *5 仿真 6 创建Testbench波形源文件 7 设置输入仿真波形 -eda
Platform: | Size: 183296 | Author: tom | Hits:

[VHDL-FPGA-Verilog] proc

Description: vhdl processor,5 commands,memory,testbench
Platform: | Size: 1229824 | Author: ulyana | Hits:

[Other] venomgen

Description: venomgen - C source code of VHDL code generator for CRC, BCH and RS encoder -venomgen- C source code of VHDL code generator for CRC, BCH and RS encoder * polynomials can be entered via command line * variable bus width * automatic testbench generation
Platform: | Size: 258048 | Author: Michael Lau | Hits:

[VHDL-FPGA-Verilog] memoryarray

Description: 由VHDL撰写的两记忆体转置程序，内含testbench与转置源码。-VHDL written by the two memory migration procedures, includes testbench and migration source.
Platform: | Size: 3072 | Author: Risger | Hits:

[VHDL-FPGA-Verilog] des

Description: des解密加密的verilog源代码其中包含有测试源代码，仿真结果图-verilog des decrypt encrypted source code which includes testing the source code, Simulation results
Platform: | Size: 343040 | Author: cong | Hits:
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